1992 EOS/ESD Symposium

Dallas, TX

Table of Contents

Session 1: Factory Issues

Session Moderator: Will McFarland, AT&T Information Systems

1.1 A Systematic ESD Program Revisited (invited), G.T. Dangelmayer, AT&T Network Systems, p1.

1.2 The Misconceptions of Air Flow as a Tribocharging Source, G. Baumgartner, Lockheed Missiles and Space Company, Inc., p9.

1.3 An Evaluation of Air Ionizers for Static Charge Reduction and Particle Emission, D.M. Fehrenbach, R.R. Tsao, Intel Corporation, p19.

1.4 Static Phenomena and Test Methods for Static Controlled Floors, S.L. Fowler, United Technical Products, Inc. and W.G. Klein, K&S Laboratories, Inc., p27.

Session 2: System Effects and Testing

Session Moderator: Douglas Smith, AT&T Bell Laboratories

2.1 ESD - A Problem Beyond the Discrete Component, G. Morin, S. Bouchard, Transients Analysis Laboratory, p39.

2.2 Techniques and Methodologies for Making System Level ESD Response Measurements for Troubleshooting or Design Verification, D. Smith, AT&T Bell Laboratories, p47.

2.3 The Resistive Phase of an Air Discharge and the Formation of Fast Risetime ESD Pulses, H.M. Hyatt, G&H Technology, Inc., p55.

2.4 From Lightning to Charged-Device Model Electrostatic Discharges, D.L. Lin and T.L. Weisher, AT&T Bell Laboratories, p68.

2.5 An Advanced ESD Test Method for Charged Device Model, M. Tanaka, M. Sakimoto, I. Nishimae, K. Ando, Hitachi, Ltd., p76.

Session 3: EOS, Oxide Damage and Reliability

Session Moderator: Henry Domingos, Clarkson University

3.1 Electrical Overstress (EOS) Power Profiles: A Guideline to Oualify EOS Hardness of Semiconductor Devices, C. Diaz, S. Kang, University of Illinois and C. Duvvury, L. Wagner, Texas Instruments, Inc., p88.

3.2 A Newly Observed High Frequency Effect on the ESD Protection Utilized In a Gigahertz NMOS Technology, H. Weston, V. Lee, T. Stanik, AT&T Bell Laboratories, p95.

3.3 ESD Induced Gate Oxide Damage During Wafer Fabrication Process, S. Kim, Intel Corporation, p99.

3.4 The Integrity of Gate Oxide Related to Latent Failures Under EOS/ESD Conditions, W. Greason, K. Chum, University of Western Ontario, p106.

3.5 Parametric Drift in Electrostatically Damaged MOS Transistors, M. Tunnicliffe, V. Dwyer, D. Campbell, Loughborough University of Technology, p112.

3.6 Annealing of ESD-Induced Damage in Power MOSFETs, D.Zupac, R. Schrimpf, K. Galloway, University of Arizona and D. Pote, Motorola, Inc., p121.

3.7 Integrated Circuit Metal in the Charged Device Model: Bootstrap Heating, Melt Damage, and Scaling Laws, T. Maloney, Intel Corporation, p129.

Session 4: Failure Mechanisms and Device Issues

Session Moderator: Michael Bridgwood, Clemson University

4.1 Paper Withdrawn, p135.

4.2 ESD Improvement Using Low Concentrations of Arsenic Implantation in CMOS Output Buffers, M. Chaine, S. Desai, C. Dunn, D. Dolby, W. Holland, T. Pekny, Texas Instruments, Inc., p136.

4.3 MOSFET Drain Engineering for ESD Performance, Y. Wei, Y. Loh, C. Wang, VLSI Technology, and C. Hu, University of California at Berkeley, p143.

4.4 Characterization and Failure Analysis of Advanced CMOS Sub-Micron ESD Protection Structures, C. Cook, S. Daniel, VLSI Technology, p149.

4.5 Paper Withdrawn, p158.

4.6 PIN Photodetectors - The ESD Bottleneck in Laser Packages, T. Diep, AT&T Bell Laboratories and S. Phatak, D. Yoo, AT&T Microelectronics, p159.

4.7 Fieldmitter-Based ESD-Protection Circuits for High Frequency Devices and IC's, K. Bock, H. Hartnagal, Technical University of Darmstadt, F.R.G., p168.

Session 5A: ESD Materials

Session Moderator: Niels Jonassen, Technical University of Denmark

5A.1 Shrink Film Packaging Evaluation, D. Hines, W.R. Grace & Co. and W. Duncan, Motorola, Inc., p175.

5A.2 Thermoformable Materials for Static Protection, A. Suopys, F. Kish, ITW Technology Center, p179.

5A.3 Inherently Dissipative Polymer Films, T. Fahey, G. Wilson, BFGoodrich Co. p189.

SA.4 A Technique for Controlling Surface Charging of Plastic and Ceramic IC Packages In the Scanning Electron Microscope by the Use of Topical Antistats, T. Marcinko, Ford Microelectronics, Inc. p195.

5A.5 Experimental Comparison of Methods of Charge Decay Measurements for a Variety of Materials, J. Chubb, John Chubb Instrumentation and P. Malinvemi, Grace ltaliana SpA, p203.

5A.6 Triboelectric Testing of Packaging Materials - Practical Considerations: What Is Important? What Does It Mean? D. Swenson, 3M Electrical Specialties Division and R. Gibson, IBM Canada Ltd., p209.

5A.7 Testing ESD Shielding Bags with an Improved Bag Tester According to EIA-541, R. Gaertner, H. Schmeer, Universitaet der Bundeswehr Muenchen, p218.

Session 5B: On-Chip Protection

Session Moderator: Ajith Amerasekera, Texas Instruments, Inc.

5B.1 On Chip Electrostatic Discharge Protections for Inputs, Outputs and Supplies of CMOS Circuits, N. Maene, J. Vandenbroeck, L. Van den Bempt, Alcatel Bell, p288.

5B.2 A Successful HBM ESD Protection Circuit for Micron and Sub-Micron Level CMOS, B. Carbajal III, R. Cline, B. Andresen, Texas lnstruments, Inc., p234.

5B.3 Dual Rail ESD Protection Using Complementary SCRs, G. Croft, Harris Semiconductor, p234.

5B.4 ESD Protection in a 3.3V Sub-Micron Silicided CMOS Technology, D. Krakauer, K. Mistry, Digital Equipment Corporation, p250.

5B.5 A Novel CMOS ESD/EOS Protection Circuit with Full-SCR Structures, M. Ker, C. Wu, National Chiao-Tung University and C. Lee, United Microelectronics Corp., p258.

5B.6 An Investigation of BICMOS ESD Protection Circuit Elements and Applications In Submicron Technologies, A. Amerasekera, A. Chatterjee, Texas Instruments, Inc., p265.

5B.7 Shallow Trench Isolation Double-Diode Electrostatic Discharge Circuit and Interaction with DRAM Output Circuitry, S. Voldman, V. Gross, M. Hargrove, J. Never, J. Slinkman, M. O'Boyle, T. Scott, J. Delecki, IBM, p277.

Workshop Session A

Session Coordinator: Rick Brin, AT&T Information Systems

WA.1 Implementing an ESD Control Program, Chair: S. Kaminskas, Biggam Enterprises, p289.

WA.2 EOS/ESD Forum on Packaging Protection: Problems and Solutions, Chair: J. Franey, AT&T Bell Laboratories, p290.

WA.3 Device Testing and On-Chip Protection: Problems and Solutions, Chair: L. Avery, David Sarnoff Research Center, p291.

Workshop Session B

Session Coordinator: Rick Brin, AT&T Information Systems

WB.1 Standards Workshop, Chair: J. Kinnear, Jr., IBM, p292.

WB.2 System/Subsystem Level ESD Issues, Chair: D. Smith, AT&T Bell Labs, p293.

WB.3 EOS/ESD Failure Analysis, Chair: L. Wagner, Texas Instruments, Inc. p294.

--------------------------------------------------------------------------------

Biographies, p295.

1992 Exhibitors List, p312.

Past Awards and Presentations, p314.

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