1994 EOS/ESD Symposium

 Las Vegas, NV

Table of Contents

Session 1: Factory, Training And Equipment

Session Moderator: Ginger Hansel, Motorola

1.1 A Successful ESD Training Program, L. Snow, T. Dangelmayer, AT&T Network Systems, p1.

1.2 Implementing An ESD Program In A Multi-National Company: A Cross-Cultural Experience, W. Tan, Advanced Micro Devices, Inc., p13.

1.3 Evaluating And Qualifying Automated Test Handlers In A Semiconductor Company, L. Ow, W. Tan, Advanced Micro Devices, Inc., p22.

1.4 lonizationForProductionTools, A. Steinman, Ion Systems, Inc., p28.

1.5 RealitiesofWristStrapMonitoringSystems, R. Kallman, Pilgrim Electric Company, p34.

1.6 Field-induced ESD From CRTS: Its Cause And Cure, J. Franey, R. Renninger, AT&T Bell Laboratories, p42.

Session 2: Device Testing

Session Moderator: Koen Verhaege, IMEC

2.1 Influence of Tester, Test Method And Device Type On CDM ESD Testing, K. Verhaege, G. Groeseneken, H. Maes, IMEC, P. Egger, Technical University Munich and H. Gieser, Fraunhofer Institute for Solid State Technology, Munich, p49.

2.2 A Correlation Study Between Different Types Of CDM Testers And "Real" Manufacturing In-Line Leakage Failures, M. Chaine, C. Liong, H. San, Texas Instruments, Inc., p63.

2.3 Influence Of Tester Parasitics On "Charged Device Model" Failure Thresholds, H. Gieser, Fraunhofer Institute for Solid State Technology, Munich and P. Egger, Technical, University Munich, p69.

2.4 Charged Device Damage Of PLCCs Inside An Antistatic Shipping Tube - A Case History, T. May, C. Robinson, M. Biegel, L. Tyler, Medtronic Micro-Rel, p85.

2.5 New Failure Mechanism Due to Non-Wired Pin ESD Stressing, M. Matsumoto, M. Ura, K. Miyamoto, Mitsubishi Electric Corporation, p90.

2.6 ESD Protection Elements During HBM Stress Tests - Further Numerical And Experimental Results, C. Russ, Technical University Munich, H. Gieser, Fraunhofer Institute for Solid State Technology, Munich, and K. Verhaege, IMEC, p96.

Session 3: On-Chip Protection

Session Moderator: David Krakauer, Digital Equipment Corporation

3.1 BI-Modal Triggering For LVSCR ESD Protection Devices, C. Diaz, G. Motley, Hewlett-Packard Company, p106.

3.2 Circuit Interactions During Electrostatic Discharge, D. Krakauer, K. Mistry, Digital Equipment Corporation and H. Partovi, NexGen, Inc., p113.

3.3 ESD Trigger Circuit, N. Tandan, Philips Semiconductors, p120.

3.4 ESD Protection In A Mixed Voltage Interface and Multi Rail Disconnected Power Grid Environment In 0.50- And 0.25-jim Channel Length CMOS Technologies, S. Voldman, IBM Microelectronics, p125.

3.5 ESD Protection Using A Variable Voltage Supply Clamp, G. Croft, Harris Semiconductor, p135.

3.6 Core Clamps For Low Voltage Technologies, S. Dabral, R. Aslett, T. Maloney, Intel Corporation, p141.

Session 4: Systems

Session Moderator: Don Lin, AT&T Bell Laboratories

4.1 Transient Fields Of ESD, D. Pommerenke, Technical University Berlin, p150.

4.2 Paper Withdrawn, p160.

4.3 Tests With Different IEC801.2 ESD Simulators Have Different Results, K. Hall, Hewlett-Packard, p161.

4.4 Impulsive EMI Effects From ESD On Raised Floor, Y. Tonoya, K. Watanabe, Tokyo Metropolitan, M. Honda, Nihon Unisys, Ltd., p164.

4.5 Clarification Of Ultra-High-Speed Electrostatic Discharge And Unification Of Discharge Model, M. Tanaka, K. Okada, M. Sakimoto, Hitachi, Ltd., p170.

4.6 Lightning Surge Voltage Limiting And Survival Properties Of Telecommunication Thyristor-Based Protectors, M. Maytum, K. Rutgers, D. Unterweger, Texas Instruments Limited,, p182.

4.7 Simulation Of A System Level Transient-Induced Latch-Up Event, R. Lewis, J. Minor, Westinghouse Electric Corporation, p193.

Session 5: Materials And Triboelectric Charging

Session Moderator: Will McFarland, AT&T Information Systems

5.1 Controlling The Variables In A Rolling Friction Triboelectricity Test Set, R. Chemelli, Bellcore, p200.

5.2 Charge Generation From Floor Materials Using A Rolling Friction Tester, E. Chase, R. Chemelli, Bellcore, p206.

5.3 CDM Events In Automated Test Handlers And Environmental Testing - A Case History, J. Bernier, S. Morrison, C. Phillips, Harris Semiconductor, p214.

5.4 Do Gases Charge? N. Jonassen, Technical University of Denmark, p221.

5.5 Electrically Conducting Polyanilines For Electrostatic Dissipation, M. Angelopoulos, J. Gelorme, J. Shaw, IBM Research Division, p226.

5.6 A New Technology In Low Tribocharging Adhesives, G. Gutman, S. Yau, R. Goetz, S. Koehn, D. Swenson, 3M, p230.

Session 6: Device and Technology Issues

Session Moderator: Steven Voldman, IBM Microelectronics

6.1 The Impact Of Technology Scaling On ESD Robustness And Protection Circuit Design, A. Amerasekera, C. Duvvury, Texas Instruments, Inc., p237.

6.2 Three-Dimensional Transient Electrothermal Simulation Of Electrostatic Discharge Protection Circuits, S. Voldman, S. Furkay, J. Slinkman, IBM Microelectronics Division, p264.

6.3 The Effect Of Oxidation Of The Poly Gate On The ESD Performance Of CMOS lCs, J. Spehar, R. Colclaser, Philips Semiconductors and C. Fledderman, The University of New Mexico, p257.

6.4 Fast Turn-On Of An NMOS ESD Protection Transistor; Measurements And Simulations, J. Luchies, J. Verweij, University of Twente and C. de Kort, Philips Research, p266.

6.5 Capacitive Coupling Effects In Spark-Gap Devices, A. Wallash, T. Hughbanks, IBM Storage Systems Division, p273.

6.6 Off-Chip Protection: Shunting Of ESD Current By Metal Fingers On Integrated Circuits And Printed Circuit Boards, D. Lin, M-C Jon, AT&T Bell Laboratories, p279.

Session 7: Failure Analysis And Case Studies

Session Moderator: Jim Colvin, WSI, Inc.

7.1 Automatic Placement Related Core ESD Failures In Sub-Micron Gate Arrays, M. Yancey, American Microsystems, Inc., p286.

7.2 A Method For The Characterization And Evaluation Of ESD Protection

Structures And Networks, M. Cavone, M. Muschitiello, R. Rivoir, M. Stucchi, Tecnopolis-CSATA Novus Ortus, Valenzano, (BA), Italy, p292.

7.3 A Comparative Study Of "Low Cost" 1.3 Jim Laser Diodes: ESD Performance, J. Wallon, G. Terol, B. Bauduin, P. Devoldere, CNET/France Telecom, p301.

7.4 Failure Analysis Of CDM Failures In A Mixed Analog/Digital Circuit,N. Maene, J. Vandenbroeck, L. Van den Bempt, Alcatel Bell, p307.

7.5 Root Cause Analysis And Packaging Enhancements To Improve Processor ESD Susceptibility, G. Calabrese, W. McCarthy, C. Stroncer, IBM Large Scale Computing Division, p315.

7.6 Failure Analysis Of CMOS PALs Exhibiting ESD-Type Polygate Short To Substrate Using A State-Of-The-Art IC Diagnostic uprober System, L. Henry, M. Mahanpour, D. Mark, Advanced Micro Devices, Inc., p324.

Workshop Session A

Workshop Coordinator: Rick Brin, AT&T Information Systems

WA.1 Obtaining Management Commitment, Panel Moderator: T. Dangelmayer, AT&T Network Systems, p335.

WA.2 Impulsive EMI From Indirect ESD, Panel Moderator: M. Honda, Nihon Unisys, Ltd., p336.

WA.3 Failure Analysis, Panel Moderator: 1. Morgan, Advanced Micro Devices, p337,

WA.4 Standards Workshop - Part A, Panel Moderators: J. Kinnear, IBM and S. Gerken, USAF, p338.

Workshop Session B

Workshop Coordinator: Rick Brin, AT&T Information Systems

WB.1 Standards Workshop - Part B, Panel Moderators: J. Kinnear, IBM and S. Gerken, USAF, p338.

WB.2 System Level ESD Issues, Panel Moderator: D. Smith, AT&T Bell Laboratories, p339.

WB.3 On-Chip Protection, Panel Moderator: A. Amerasekera, Texas Instruments, Inc., p340.

--------------------------------------------------------------------------------

Biographies, p341.

Past Awards and Presentations, p359

1994 Exhibitors List, p362.

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