1993 EOS/ESD Symposium
Lake Buena Vista, FL
Table of Contents
Keynote Address
K.1 Smart Power Technology: An Elephantine Opportunity, Prof. B. Jayant Baliga, Power Semiconductor Research Center, North Carolina State University, p1.
Session1: Testing/Systems
Session Moderator: David M. Staggs, Dell Computer
1.1 A New Type Of Furniture ESD And Its Implications, D. Smith, AT&T Bell Laboratories, p3.
1.2 Impulsive ESD Noise Occurred From An Office Chair, Y. Tonoya, Tokyo Metropolitan Industrial Research Center, M. Ono, Tokyo Eastem-Distdcts, Technical Center and M. Honda, Nihon Unisys, Ltd., p9.
1.3 High Voltage Calibration For ESD Diagnostics, H. Hyatt, Hyger Physics, Inc., p17.
1.4 Paper Withdrawn ,p27.
1.5 Electrostatic Discharge Analyses For Spacecraft In Geosynchronous Orbit, R. Perez, Jet Propulsion Laboratory, p29.
Session2: Factory Issues/Control Programs
Session Moderator: Joanne Woodward-Jack, Northern Telecom
2.1 Setting Up An Effective Corporate ESD Program, R. Braude, Hewlett-Packard Company, p35.
2.2 Paper Withdrawn, p39.
2.3 You've Implemented An ESD Program - What's Next? W. McFarland, R. Brin, AT&T Global Business Communications Systems - Denver Works, p39.
2.4 Extent And Cost Of EOS/ESD Damage In An IC Manufacturing Process, R. Wagner, C. Hawkins, University of New Mexico and J. Soden, Sandia National Laboratories, p49.
2.5 Minimizing ESD Hazards In IC Test Handlers And Automatic Trim/Form Machines, W. Tan, Advanced Micro Devices, Inc., p57.
2.6 Periodic Verification Of Air Ionizer Performance, A. Steinman, Ion Systems, Inc., p65.
Session 3: EOS/Reliability/Latency/Modeling
Session Moderator: Jim Colvin, WSI, Inc.
3.1 ESD Sensitivity And VLSI Technology Trends: Thermal Breakdown and Dielectric Breakdown, D. Lin, AT&T Bell Laboratories, p73.
3.2 Studies Of EOS Susceptibility in 0.6 um NMOS ESD 1/0 Protection Structures, C. Diaz, S. Karig, University of Illinois at Urbana-Champaign and C. Duvvury, Texas Instruments, Inc., p83.
3.3 AC And Transient Latchup Characteristics Of A Twin-Well CMOS Inverter With Load Capacitance, R. Consiglio, LSI Logic Corporation, p93.
3.4 Electrostatic Failure Of GaAs Planar Doped Barrier Diodes, Y. Anand, M/A-COM, Inc. and R. Malk, AT&T Bell Laboratories, p103.
3.5 The Identification And Analysis Of Latent ESD Damage On CMOS Input Gates, J. Colvin, WSI, Inc., p109.
3.6 Suppression Of Soft Failures In A Submicron CMOS Process, F. Kuper, J. Bruines, Philips Semiconductors and J. Luchies, MESA Research Institute, University of Twente, p117.
3.7 EOS Induced Polysilicon Migration in VLSI Gate Arrays, S. Kiefer, R. Milbum, K. Rackley, Motorola, Inc., ASIC Division, p123.
Session 4: Device Testing and Failure Analysis
Session Moderator: Ajith Amerasakera, Texas Instruments, Inc.
4.1 Analysis Of HBM ESD Testers And Specifications Using A 4th Order Lumped Element Model, K. Verhaege, P. Roussel, G. Groeseneken, H. Maes, IMEC, H. Gieser, C. Russ, P. Egger, Technische Universitat Munchen, X. Guggenmos, Siemens AG and F. Kuper, Philips Semiconductors, p129.
4.2 Coaxial Probe To Measure ESD Voltage Waveforms With One Nanosecond Risetimes, W. Boxleitner, B. Corrder, KeyTek Instrument Corporation, p139.
4.3 A Statistical Method For The Detection Of Gate Oxide Breakdowns Due To Fast EOS Events, Such As ESD, On Power DIMOS Devices, G. Biermann, Siemens AG, Semiconductor Group, p143.
4.4 Characterization Of New Failure Mechanisms Arising From Power-Pin ESD Stressing, C. Cook, S. Daniel, VLSI Technology, Inc., p149.
4.5 Two-Dimensional Electrothermal Simulations And Design Of Electrostatic Discharge (ESD) Protection Circuit, S. Hong, J. Kim, T. Won, Inha University and K. Yoo, G. Kwon, Samsung Electronics, Ltd., p157.
Session 5A: Materials
Session Moderator: Steve Fowler, Optimum Solutions, Inc.
5A.1 About The Effectiveness Of Grounding Chains On Carts And The Unexpected Behaviour Of Insulating Wheels, E. Krog-Jensen, Ericsson Telecom AB and L. Hjam, ESD-Management AB, p165.
5A.2 Expanded Evaluation Of Static Protective Shrink Wrap Film, B. Hoffman, J. Redden, A. Hughes, Motorola and D. Hines, Cryovac Division, W. R. Grace & Co., p173.
5A.3 Selecting Materials For Protection Against ESD Using An ESD Shielding Effectiveness Meter, C. Borgmans, DSM Polymers, S. Gerteisen, DSM Engineering Plastics, L. Steenbakkers, DSM Research, J. Catrysse, KIH West Vlaanderen and L. Anaf, Bekaert BFT, p177.
5A.4 Performance-Oriented Design And Test Procedures For Static Control Footwear, W. Klein, K&S Laboratories, Inc., p183.
5A.5 ESD Packaging: An Environmental Perspective, J. Bradford, Bradford Company, p201.
Session 5B: On-Chip Protection
Session Moderator: Reg Wilcox, IBM
5B.1 ESD Protection Of BICMOS Integrated Circuits Which Need To Operate In The Harsh Environments Of Automotive Or Industrial, M. Corsi, R. Nimmo, F. Fattori, Texas Instruments, Limited, p209.
5B.2 The ESD Protection Capability Of SOI Snapback NMOSFETS: Mechanisms And Failure Modes, K. Verhaege, G. Groeseneken, H. Maes, IMEC and J. Colinge, UCL, p215
5B.3 Effect Of Substrate Contact On ESD Failure Of Advanced CMOS Integrated Circuits, Y. Wei, Y. Loh, C. Wang, VLSI Technology, Inc. and C. Hu, University of California at Berkeley, p221.
5B.4 Two Unusual HBM ESD Failure Mechanisms On A Mature CMOS Process, C. Johnson, T. Maloney, S. Qawami, Intel Corporation, p225.
5B.5 ESD Design Methodology, R. Merrill, E. lssaq, National Semiconductor, Fairchild Research Center, p233.
5B.6 Designing On-Chip Power Supply Coupling Diodes For ESD Protection And Noise Immunity, S. Dabral, R. Asleft, T. Maloney, Intel Corporation, p239.
5B.7 Scaling, Optimization and Design Considerations Of Electrostatic Discharge Protection Circuits In CMOS Technology, S. Voldman, V. Gross, IBM Technology Products, p251.
Workshop Session A
Session Coordinator: Rick Brin, AT&T Global Business Communications Systems - Denver Works
WA.1 Implementing An ESD Control Program, Panel Moderator: S. Karrinskas, p261.
WA.2 Failure Analysis, Panel Moderator: I. Morgan, Advanced Micro Devices, p262.
WA.3 EMI Aspects Of ESD, Panel Moderator: M. Honda, Nihon Unisys, Ltd. p263.
Workshop Session B
Session Coordinator: Rick Brin, AT&T Global Business Communications Systems - Denver Works
WO.1 Maintaining A Control Program Through An Auditing Process, Panel Moderator: D. Long, Julie Associates, Inc., p264.
WB.2 Device Testing and On-Chip Protection, Panel Moderator: L. Avery, David Sarnoff Research Center, p265.
WB.3 System/Subsystem Level ESD Issues, Panel Moderator: D. Smith, AT&T Bell Laboratories, p266.
WB.4 Standards Showcase, Panel Moderator: J. Kinnear, IBM, p267.
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Biographies, p269.
1993 Exhibitors List, p286.
Past Awards and Presentations, p288.
