1995 EOS/ESD Symposium, Phoenix, AZ
Table of Contents
Session Moderator: Ajith Amerasekera, Texas Instruments
1.1 Novel Clamp Circuits For IC Power Supply Protection, T. Maloney, S. Dabral, Intel Corporation, p1.
1.2 Sub-Micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions, E. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen, M. Tennyson, Rockwell Telecommunications, p13.
1.3 A Novel ESD Protection Technique For Submicron CMOS/BICMOS, K. Kwon, H. Park, D. Kim, K. Park, J. Jin, S. Lim, Samsung Electronics Co., Ltd., p21.
1.4 Punchthrough Transient Voltage Suppressor For EOS/ESD Protection of Low-Voltage lCs, Yu, Y.-C. King, C. Hu, University of California at Berkeley, J. Pohlman, Semtech Corporation, p27.
1.5 Impact Of 1/0 Buffer Configuration On The ESD Performance Of A 0.5 um CMOS Process, Nikolaidis, C. Papadas, M. Varrot, P. Mortini, SGS-THOMSON Microelectronics, G. Pananakakis, L.P.C.S.-E.N.S.E.R.G. p34.
1.6 Analysis Of Snubber-Clamped Diode-String Mixed Voltage Interface ESD Protection Network For Advanced Microprocessors, S. Voldman, V. Gross, S. Furkay, J. Slinkman, IBM Microelectronics Division, G. Gerosa, Somerset Design Center, N. Dickson, Motorola, Inc. p43.
Session Moderator: John Kinnear, IBM
2.1 Why Does The FDA Concern Itself With ESD? E. O'Bryan, Food and Drug Administration (FDA), p62.
2.2 Spacecraft And Human Electrostatic Discharge: A Comparison Of The Two Phenomena, K. Balmain, University of Toronto, p66.
2.3 Human Body Electrostatic Charge (ESC) Levels: Are They Limited By Corona Bleed Off Or Environmental Conditions? K. Katrak, General Motors Proving Ground, p73.
2.4 New Approaches To Indirect ESD Testing, M. Honda, Nihon Unisys, Ltd., T. Kinoshita, EMC Study Group, p86.
2.5 Human Hand/Metal ESD And Its Physical Simulation, R. Saini, K. Balmain, University of Toronto, p90.
2.6 Calculation And Measurement Of Transient Fields Of Voluminous Objects, R. Zaridze, D. Karkashadze, Tbilisi State University, R. Djobava, Suchumi University, D. Pommerenke, M. Aidam, Technical University Berlin, p95.
2.7 To What Extent Do Contact-Mode And Indirect ESD Test Methods Reproduce Reality?, D. Pommerenke, M. Aidam, Technical University Berlin, p101.
Session 3: Factory Issues and ESD Training
Session Moderator: Wayne Tan, Advanced Micro Devices, Inc.
3.1 ESD Improvements For Familiar Automated Handlers, J. Bernier, B. Hesher, Harris Semiconductor, p110.
3.2 Sporadic Effect Of Leadscan Machine To CMOS ESD Low Yielding Lots, R. Almazar, Motorola Phils Inc., SPS, p118.
3.3 ESD Measurements And Corrective Actions For Integrated Circuits (IC) Lead Inspection/Handling Systems, A. Soto, J. Delage, MOS Digital Analog Motorola, p124.
3.4 Effectiveness of ESD Training Using Multimedia, G. Smalanskas, Digital Equipment Corporation, J. Mason, Interactive Media Communications, p129.
3.5 ESD Control Program: A Viewpoint From The Receiving End, T. Koay, W. Tan, Advanced Micro Devices, p134.
3.6 Resistance To Ground And Tribocharging Of Personnel, As Influenced By Relative Humidity, D. Swenson, 3M, J. Weidendorf, D. Parkin, E. Gillard, IBM, p141.
3.7 ESD Flooring: An Engineering Evaluation, D. Robinson-Hahn, AT&T Microelectronics, p154.
Session 4: Device Testing and Protection Circuits
Session Moderator: Koen Verhaege, IMEC
4.1 Advanced CMOS Protection Device Trigger Mechanisms During CDM, C. Duvvury, A. Amerasekera, Texas Instruments, Inc. p162.
4.2 A Comparison Of Electrostatic Discharge Models and Failure Signatures For CMOS Integrated Circuit Devices, M. Kelly, G. Servais, Delco Electronics Corporation, T. Diep, D. Lin, AT&T Bell Laboratories, S. Twerefour, Ford Microelectronics, Inc., G. Shah, Ford Motor Company, p175.
4.3 Study Of ESD Evaluation Methods For Charged Device Model, T. Wada, Matsushita Electronics Corporation, [Best Paper Award Winner: 1994 EOS/ESD Symposium, Japan], p186.
4.4 Transient-induced Latchup Testing Of CMOS Integrated Circuits, G. Weiss, AT&T Bell Laboratories, D. Young, AT&T Global Manufacturing and Engineering, p194.
4.5 ESD Reliability Impact Of P+ Pocket Implant On Double Implanted NLDD MOSFET, R.Consiglio, T. Huang, VLSI Technology Inc., p199.
4.6 Layout Optimization Of An ESD-Protection N-MOSFET By Simulation And Measurement, A. Stricker, W. Fichtner, Swiss Federal Institute of Technology, D. Gloor, Philips Components, p205.
4.7 EOS/ESD Protection Circuit Design For Deep Submicron SOI Technology, S. Ramaswamy, P. Raha, E. Rosenbaum, S. Kang, University of Illinois at Urbana-Champaign, p212.
Session 5: ESD Control Materials and Measurements
Session Moderator: Will McFarland, AT&T
5.1 Use Of Static-Safe Polymers In Automated Handling Equipment, R. Campbell, The Polymer Corporation, W. Tan, Advanced Micro Devices, Inc., p218.
5.2 Cross-Linkable Conducting Polymer Coatings, V. Kulkarni, Americhem, Inc., M. Angelopoulos, IBM, p25.
5.3 Electrically Conductive Polypropylene-Polyaniline Blend In ESD Protection, K. Vakiparta, P. Kirmanen, J. Laakso, P. Passiniemi, T. Taka, E. Virtanen, Neste Oy, p229.
5.4 Carbon Loaded Device Handling Trays: Analysis And Measurements, W. Tan, Advanced Micro Devices, Inc., p236.
5.5 Best Practices For Applying Air Ionization, A. Steinman, Ion Systems, Inc., p245.
5.6 A Method For Measurement Of Triboelectric Charging, A. Borjesson, SP-Swedish National Testing and Research Institute, p253.
5.7 Electrostatic Decay Measurement Theory And Applications, G. Baumgartner, Lockheed Martin Missiles and Space, p262.
Session Moderator: Don Lin, AT&T Bell Laboratories
6.1 Failure Analysis Of Shallow Trench Isolated ESD Structures, J. Never, S. Voldman, IBM Microelectronics Division, p273.
6.2 The Correlation Between Latch-Up Phenomenon And Other Failure Mechanisms, M. Mahanpour, I. Morgan, Advanced Micro Devices, Inc. 289.
6.3 Melt Filaments In n+pn+ Lateral Bipolar ESD Protection Devices, N. Clark, K. Parat, T. Maloney, Y. Kim, Intel Corporation, p295.
6.4 Quantifying ESD/EOS Latent Damage And Integrated Circuit Leakage Currents, M. Song, D. Eng, K. MacWilliams, The Aerospace Corporation, p304.
6.5 Latent Gate Oxide Defects Caused By CDM-ESD, J. Reiner, Swiss Federal Institute of Technology, p311.
6.6 ESD Failure Mechanisms Of Inductive And Magnetoresistive Recording Heads, A. Wallash, T. Hughbanks, IBM Storage Systems Division, S. Voldman, IBM Microelectronics Division, p322.
Session 7: Electrostatic Considerations In Industry
Session Moderator: David Swenson, 3M
7.1 Explosions And Static Electricity, N. Jonassen, Technical University of Denmark, p331.
7.2 Case Study - Electrostatic Problems In The Graphic Arts Industry (Non-Published Paper), E. Weggeland, Richmond Plastics
7.3 ESD - An Explosive Subject?, D. Hale, Douglas E. Hale & Associates Pty., Ltd., p338.
7.4 A Plastic Induced ESD Failure (Non-Published Paper), J. Kinnear, IBM Corporation
7.5 Machine Model ESD Failure In A Manufacturing Environment (Non-Published Paper), R. Gibson, Celestica, Inc.
7.6 Case Study - Evaluation Of ESD As A Potential Ignition Source Of Pressurized Air Force Missile Shipping Containers Due To Packaging Foams That Outgas Flammable Blowing Agents (Non-Published Paper), S. Gerken, US Air Force
7.7 Case Study - Large Plastic Web Electrostatic Problems, Results And Cure (Non-Published Paper), D. Swenson, 3M Company
Workshop Chairman: Rick Brin, AT&T Information Systems
WA.1 ESD Auditing Problems, Moderator: L. Fromm, Hewlett Packard, p347.
WA.2 System Level ESD Workshop, Moderator: M. Hopkins, Thermo Voltek Corporation, p348.
WA.3 Failure Analysis Workshop, Moderator: D. Lin, AT&T Bell Laboratories, p349.
Workshop Coordinator: Rick Brin, AT&T Information Systems
WB.1 Standards Workshop, Moderator: S. Gerken, US Air Force, p350.
WB.2 Electrostatic Considerations In The Cleanroom, Moderator: E. Williams, Richmond Static Control Services, p351.
WB.3 On-Chip Protection, Moderator: T. Maloney, Intel Corporation, p352.
Biographies, p353.
Past Awards and Presentations, p373.
1995 Exhibitors List, p378.
