1996 EOS/ESD Symposium
Orlando, FL
Table of Contents
Session1: MR Heads and Related ESD Issues
Session Moderator: Albert J. Wallash, Quantum
1.1 An Investigation of ESD Protection for Magnetoresistive Heads, T. Cheung, A. Rice, Applied Magnetics Corporation, p1.
1.2 Field-induced Charged Device Model Testing of Magnetoresistive Recording Heads, A. Wallash, Quantum, p8.
1.3 Characterization of ESD Tweezers for Use With Magnetoresistive Recording Heads, C. Lam, Read-Rite Corporation, p14.
1.4 Static Charge Control Issues for Disk Drive Production Using MR Heads, A. Steinman, Ion Systems, Inc. p22.
1.5 ESD Induced Capacitor Shorts, E. Weaver, C. Yots, Texas Instruments, Inc., p28.
1.6 A Low Cost Visual Indicator for Detecting Ground Connection Failure of CRT Filter Screens, G. Chase, Bellcore; J. Patel, The Pennsylvania State University, p32.
Session 2: Device, Testing and Failure Analysis
Session Moderator: Koen Verhaege, David Sarnoff Research Center
2.1 Recommendations to Further Improvements of HBM ESD Component Level Test Specifications, K. Verhaege, David Sarnoff Research Center; C. Russ, G. Groeseneken, IMEC; D. Robinson-Hahn, D. Lin, Lucent Technologies; M. Farris, Intel; J. Scanlon, American Systems Corporation; J. Veltri, Digital, p40.
2.2 CDM ESD Test Considered Phenomena of Division and Reduction of High Voltage Discharge in the Environment, M. Tanaka, K. Okada, Hitachi, Ltd., p54.
2.3 A Combined Socketed and Non-Socketed CDM Test Approach for Eliminating Real-World CDM Failures, A. Olney, Analog Devices, Inc., p62.
2.4 ESD and Latch Up Phenomena on Advanced Technology LSI, Y.Fukuda, K. Kato, E. Umemura, OKI Electric Industry Co., Ltd., p76.
2.5 Very-Fast Transmission Line Pulsing of Integrated Structures and the Charged Device Model, H. Gieser, M. Haunschild, Fraunhofer-Institut Festkorpertechnologie, p85.
2.6 Identification of Electrical Over Stress Failures from Other Package Related Failures Using Package Delamination Signatures, S. Li, K. Lee, J. Hulog, S. Kazmi, S. Yin, J. Pollock, Advanced Micro Devices, p95.
2.7 Linewidth Control Effects on MOSFET ESD Robustness, S. Voldman, J. Never, S. Holmes, J. Adkisson, IBM Microelectronics Division, p101.
Session3: Factory and Training Issues
Session Moderator: John Kinnear, Jr., IBM
3.1 Immediate Elimination of Gross ESD Failures in PLCC MECL Product Line Through Innovative Techniques, R. Almazar, B. Hoffman, Motorola-Philippines, Inc., p110.
3.2 Die Level CDM Testing Duplicates Assembly Operation Failures, J. Bernier, G. Croft, Harris Semiconductor, p117.
3.3 Interconnects For Device ESD Protection, T. Jarrett, Cardiac Pacemakers, Inc.; B. Unger, CRO-BAR, Inc., p123.
3.4 ESD Protection Measures Return on Investment Calculation and Case Study, K. Helling, Siemens AG, p130.
3.5 Developing an Exit Charge Specification for Production Equipment, A. Steinman, Ion Systems, Inc.; J. Montoya, Intel Corporation, p145.
3.6 Alternate Uses for the Charged Plate Monitor, W. Vosteen, Monroe Electronics, Inc., p150.
3.7 ESD Demonstrations to Increase Engineering & Manufacturing Awareness, G. Baumgartner, Lockheed Martin Missiles & Space, p156.
Session 4: System Effects of ESD
Session Moderator: Dr. David Pommerenke, University of Berlin
4.1 Charged Device Model (CDM) Metrology: Limitations and Problems, L.G. Henry, Advanced Micro Devices; H. Hyatt, Hyger Physics, Inc.; J. Barth, Barth Electronics, Inc.; M. Stevens, Motorola; T. Diep, Texas Instruments, p167.
4.2 What is a Real 1 GHz Bandwidth ESD Generator Calibration?, P. Glaftli, Swiss Telecom PTT, p180.
4.3 One of the Methods of Observing ESD Around Electronic Equipments, T. Takai, M. Kaneko, Hitachi Electronics Services Co., Ltd.; M. Honda, Impulse Physics Laboratory, Inc., p186.
4.4 Non-invasive Detection and Characterization of ESD Induced Phenomena in Electronic Systems, W. Greason, S. Bulach, M. Flatley, University of Western Ontario, p193.
4.5 Numerical Calculation of ESD, R. Jobava, D. Karkashadze, R. Zaridze, P. Shubitidze, Tbilisi State University; D. Pommerenke, Technical University Berlin; M. Aidam, Technical University Munich, p203.
4.6 Measurements of ESD HBM Events, Simulator Radiation and Other Characteristics Toward Creating a More Repeatable Simulation or; Simulators Should Simulate, J. Barth, Barth Electronics, Inc.; D. Dale, K. Hall, D. McCarthy, Hewleff Packard; H. Hyatt, Hyger Physics, Inc.; J. Nuebel, Sun Microsystems; D. Smith, Auspex Systems, p211.
4.7 An Investigation into the Performance of the IEC 1000-4-4 Capacitive Clamp, D. Smith, Auspex Systems, p223.
Session 5: ESD Materials and Testing
Session Moderator: Donna Robinson-Hahn, Lucent Technologies
5.1 Vanadium Pentoxide Based Antistatic Coatings, N. Somasiri, V. Talbot, W. Clatanoff, E. Morrison, 3M Company, p227.
5.2 Comparison of Several Anti-Static Surfactant Coatings for Plastics, C. Extrand, Fluoroware, p232.
5.3 Antistatic Masking Tapes for Solder Flux Reflow Processing of Printed Circuit Boards, A. Ball, S. Yau, G. Gutman, D. Swenson, 3M/Electrical Specialties Division, p241.
5.4 A Hybrid Technology: Static Dissipative/VCI Films, B. Rudman, C. Chandler, Cortec Corporation, p248.
5.5 New Charged-Plate Monitor Design Offers Greater Flexibility, D. Zacher, Trek, Inc., p254.
5.6 Some Results in Measuring Static Decay, B. Ehrmaier, H. Schmeer, Universitaet der Bundeswehr Muenchen, p259.
Distinguished Guest Speaker, Fred W. Haise, "Survival in Space, Apollo 13"
Session 6: On-Chip Protection and Simulation
Session Moderator: Dr. Leo G. Henry, Advanced Micro Devices
6.1 Methodology for Layout Design and Optimization of ESD Protection
Transistors, S. Beebe, Advanced Micro Devices, p265.
6.2 Transient Supply Clamp with a Variable RC Time Constant, G. Croft, Harris Semiconductor, p276.
6.3 Study of Gated PNP as an ESD Protection Device for Mixed-Voltage and Hot-Pluggable Circuit Applications, M. Tong, R. Gauthier, V. Gross, IBM Microelectronics Division, p280.
6.4 EOS/ESD Analysis of High-Density Logic Chips, S. Ramaswamy, S. Kang, University of Illinois at Urbana-Champaign; C. Duvvury, A. Amerasekera, V. Reddy, Texas Instruments, Inc., p285.
6.5 CMOS-ON-SOI ESD Protection Networks, S. Voldman, R. Schulz, J. Howard, V. Gross, S, Wu, A. Yapsir, D. Sadana, H. Hovel, J. Walker, F. Assaderaghi, B. Chen, J.Y-C Sun, G. Shahidi, IBM, p291.
6.6 A Compact Model for the Grounded-Gate NMOS Behaviour Under CDM ESD
Stress, C. Russ, K. Bock, P. Roussel, G. Groeseneken, H. Maes, IMEC; K. Verhaege, David Sarnoff Research Center, p302.
6.7 Circuit-Level Simulation of CDM-ESD and EOS in Submicron MOS Devices, S. Ramaswamy, E. Li, E. Rosenbaum, S. Kang, University of Illinois at Urbana-Champaign, p316.
Session 7: ESD Considerations In Industry
Session Moderator: David E. Swenson, 3M
7.1 The ESD Threat, D.K. Davies, Markab, p322.
7.2 Study of ESD Ouench Effects by Air Ionization, M. Honda, Impulse Physics Laboratory, Inc.; T. Murakami, Harada Corporation; Y. Tonoya, Tokyo Metropolitan Industrial Research Center, p327.
7.3 Control of Static Charge on Personnel: Impact of Socks on Resistance to Ground Through Footwear, T. Numaguchi, Sumitomo 3M, Limited (Japan), p333.
7.4 Functional Methods to Determine the EPA Compatibility of Mechanical Tools, J. Thurmer, 3M Laboratories (Europe) GmbH, p338.
7. 5 Detection Hazards Caused by ESD - Case Study, Hazards in Silos, L. Ptasinski, T. Zeglen, University of Mining and Metallurgy; A. Gajewski, Cracow Academy of Economy, p351.
7.6 The Effect of Static Charge Generated on Hospital Bedding, P. Holdstock, N. Wilson, British Textile Technology Group, p356.
7.7 Electrostatic Problems in TFT-LCD Production and Solutions Using Ionization, T. Murakami, H. Togari, Harada Corporation, A. Steinman, Ion Systems, Inc., p365.
