1998 EOS/ESD Symposium
Reno, NV
Table of Contents
Session 1A: Materials
Session Moderator: Donna Robinson-Hahn, Lucent Technologies
1A.1 New Injection Moldable ESD Compounds Based on Very Low Carbon Black Loadings, M. Narkis, Technion-IIT; G. Lidor, A. Vaxman, L. Zuri, Carmel Olefins, Ltd., p1.
1A.2 Paper Withdrawn
1A.3 Evaluation of Cleanroom/ESD Garment Fabrics: Test Methods and Results, W. Boone, Maxtor Corporation, p10.
1A.4 Controlling ESD and Absorbing and Shielding EMW by Using Conductive Fiber in Aircraft, T. Hiramoto, T. Terauchi, J. Tomibe, Nihon Sanmo Dyeing Co., Ltd., p18.
Session 1B: System Level ESD Issues
Session Moderator: Don Lin, Lucent Technologies
1B.1 ESD Events in Aircraft Cabin Environment, M. Honda, Impulse Physics Laboratory, Inc., p22.
1B.2 An ESD Characterization Method for System Level Surge Arrestors, Paper Not Available at Press Time
1B.3 Metrology & Methodology of System Level ESD Testing, D. Lin, Lucent Technologies; D. Pommerenke, Hewlett Packard; J. Barth, Barth Electronics, Inc.; L.G. Henry, AMD (now Oryx); H. Hyatt, Hyger Physics, Inc.; M. Hopkins, G. Senko, KeyTek; D. Smith, Auspex Systems, p29.
1B.4 An Experimental and Theoretical Consideration of Physical Design Parameters in Field-induced Charged Device Model ESD Simulators and Their Impact Upon Measured Withstand Voltages R.Carey, Lucent Technologies Microelectronics Group; L. DeChiaro, Lucent Technologies ERC, p40.
Session 2A: On-Chip Protection Circuits
Session Moderators: Steven Voldman, IBM; Yehuda Smooha, Lucent Technologies
2A.1 ESD Protection for Mixed Voltage I/O Using NMOS Transistors Stacked in a Cascode Configuration, W. Anderson, Digital Equipment Corporation; D. Krakauer, p54.
2A.2 A Substrate Triggered Lateral Bipolar Circuit for High Voltage Tolerant ESD Protection Applications, J.Smith, Motorola, p63.
2A.3 How to Safely Apply the LVTSCR for CMOS Whole-Chip Protection without being Accidentally Triggered On, M. Ker, ITRI; H. Chang, TSMC, p72.
2A.4 Paper Withdrawn.
2A.5 Cross-Referenced ESD Protection for Power Supplies, W. Anderson, Digital Equipment Corporation; J. Montanaro, Cadence Design Systems, Inc.; N. Howorth, Intel, p86.
2A.6 High Voltage Resistant ESD Protection Circuitry for 0.5um CMOS OTP/EPROM Programming Pin, H. Schrbder, G. van Steenwijk, G. Notermans, Philips Semiconductors, p96.
2A.7 A Simulation Study of HBM Failure in an Internal Clock Buffer and the Design Issues for Efficient Power Pin Protection Strategy, V.Puvvada, C. Duvvury, Texas Instruments, Inc., p104.
Session 2B: General ESD Considerations
Session Moderator: Joe Bernier, Harris Semiconductor
2B.1 Human Body Capacitance: Static or Dynamic Concept?, N. Jonassen, Technical University of Denmark, p111. As
2B.2 Electrostatic Discharges From Charged Particles Approaching a Grounded Surface, L. Dascalescu, P. Ribardiere, C. Duvanaud, J. Paillot, lnstitut Universitaire de Technologie d'Angouldeme, p118.
2B.3 Outgassing, Volatile Organic Content, and Contamination Content of Materials Used in Today's Electronics Workplace, L. Cohen, Static Solutions Inc.; S. Blankstein, ACL Staticide Inc. p124.
2B.4 Electrostatic Build Up on Metal Balls Due to Sliding Contact With Insulating Materials and How to Reduce It With Carbon-Fiber Reinforced Plastics - Electrostatic Discharge in Pachinko Parlors,K.Nakanishi, Osaka Gas Chemicals Co., Ltd. p128.
2B.5 Discussion on Electric Parameters of Standard for Anti-Electrostatic Floor, W. Zonghan, C. Quan, W. Yue, Southeast University; S. Jian, Nanjing Power College; F. Jianping, L.Bin, San-jin Anti-Electrostatic Instrument Factory; S. Caikang, Institute of Architecture Engineering; J.Xiaobing, Institute of Post and Telecommunication, p135.
2B.6 Electrostatic Hazards Of Explosive, Propellant and Pyrotechnic Powders, J. Dahn, B. Reyes, A. Kashani, J. Finkelshtein, Safety Consulting Engineers, Inc. p139.
Session 3A: Semiconductor Process and Device Issues
Session Moderators: Fred Kuper, Philips Semiconductors; Eugene Worley, Rockwell International
3A.1 Semiconductor Process and Structural Optimization of Shallow Trench Isolation Defined and Polysilicon-Bound Source/Drain Diodes for ESD Networks, S.Voldman, S. Geissler, J. Nakos, J. Pekarik, R. Gauthier, IBM, p151.
3A.2 ESD-Related Process Effects in Mixed-Voltage Sub-0.5 ILm Technologies, V.Gupta, A. Amerasekera, S. Ramaswamy, A. Tsao, Texas Instruments, Inc., p161.
3A.3 Pitfalls When Correlating TLP, HBM, and MM Testing, G. Notermans, P. de Jong, F. Kuper, Philips Semiconductors, p170.
3A.4 Non-Uniform Triggering of gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Testing, C. Russ, K. Bock, M. Rasras, I. De Wolf, G. Groeseneken, H. Maes, IMEC, p177.
3A.5 Investigations on the Thermal Behavior of Interconnects Under ESD Transients Using a Simplified Thermal RC Network, P. Salome, STMicroelectronics; C. Leroux, CEA Technologies Avancees; P. Crevel, MHS-Route de Gachet; J.-P. Chante, CEGELY-ECPA-INSA, p187.
3A.6 ESD and Latch-up Characteristics of Semiconductor Device with Thin Epitaxial Substrate, T. Suzuki, S. Sekino, S. Ito, H. Monma, Fujitsu Limited, p199.
3A.7 An Automated Tool for Detecting ESD Design Errors, S. Sinha, H. Swaminathan, G. Kadamati, C. Duvvury, Texas Instruments, Inc., p208.
Session 3B: Factory Issues
Session Moderator: Larry Fromm, Hewlett Packard
3B.1 Measures Against Electrostatic Destruction of Electronic Devices at Electronic Equipment Assembly Shops (invited - Best Paper RCJ 1997 EOS/ESD Symposium, Japan), K.Saotome, K. Matsuhashi, NEC Saitama, Ltd., p218.
3B.2 EOS Analysis of Soldering Iron Tip Voltage, G. Baumgartner, J. Smith, Lockheed Martin, p224.
3B.3 Magneto Optical Static Event Detector, N. Jacksen, ExMod Corporation; W. Tan, AMD; D. Boehm, Novx Corporation, p233.
3B.4 Wrist Strap Designs and Comparison of Test Results According to MIL-PRF-87893 and ANSI EOS/ESD Association Sl.l, T. Namaguchi, H. Uchida, Sumitomo/3M Limited, p245.
3B.5 Charge Trap Phenomena on EPROM Device - Methodology to Identify the Cause of the Problem in IC Manufacturing Process to Improve Electrical Test Yield, I. Omar, Motorola, p252.
3B.6 Paper Withdrawn
Session 4A: Device and Circuit Simulation and Tester Issues
Session Moderators: Koen Verhaege, Sarnoff Corporation; Michael Chaine, Texas Instruments
4A.1 Simulation of Complete CMOS 1/0 Circuit Response to CDM Stress, S. Beebe, Advanced Micro Devices, p259.
4A.2 Bipolar Model Extension for MOS Transistors Considering Gate Coupling Effects in the HBM ESD Domain, H.Wolf, Technische Universitit Monchen; H. Gieser, Fraunhofer-Institut Festkbrpertechnologie; W.Stadler, Siemens AG, p271.
4A.3 Substrate Resistance Modeling and Circuit-Level Simulation of Parasitic Device Coupling Effects for CMOS 1/0 Circuits Under ESD Stress, T. Li, C. Tsai, E. Rosenbaum, S. Kang, University of Illinois at Urbana-Champaign, p281.
4A.4 Characterization and Optimization of a Bipolar ESD-Device by Measurements and Simulations, A. Stricker, W. Fichtner, Swiss Federal Institute of Technology; S. Mettler, M. Mergens, W. Wilkening, Robert Bosch Gmbh; H. Wolf, H. Gieser, Fraunhofer-Institut Festkbrpertechnologie, p290.
4A.5 Investigation Into Socketed CDM (SDM) Tester Parasitics, M. Chaine, Texas Instruments, Inc.; K. Verhaege, L. Avery, Sarnoff Corporation; M. Kelly, Delphi DelGo, Electronics Systems; H. Gieser, IFT Fraunhofer Institute Festkbrpertechnologie; K. Bock, IMEC; L.G. Henry, ORYX Instruments Corporation; T. Meuse, KeyTek; T. Brodbeck, Siemens AG; J. Barth, Barth Electronics, Inc. p301.
4A.6 Ultra Low Impedance Transmission Line Tester, C. Chu, E. Worley, Rockwell Semiconductor Systems, p311.
4A.7 Influence of the Device Package on the Results of CDM Tests - Consequences for Tester Characterization and Test Procedure, A. Kagerer, T. Brodbeck, Siemens AG, p320.
Session 4B: MR Heads
Session Moderator: Al Wallash, Quantum
4B.1 Current Transients and the Guzik: A Case Study and Methodology for Qualifying a Spin Stand For GMR Testing, J. Himle, R. Bailey, J. Hogue, R. McKenzie, T. Porter, W. Boone, Maxtor Corporation; A. Fishman, Guzik Enterprises, p328.
4B.2 Ion Milling Induced ESD Damage During MR Head Fabrication
D.Olson, C. Chang, Seagate Technology, p332.
4B.3 Evaluation of Wrist Strap Monitors from an MR Head Perspective, F. Goceman, M. Szymanski, MKE-Quantum Corporation LLC; J. Salisbury, M. Sanchez, Semtronics Corporation, p341.
4B.4 ESD Prevention on an Unshunted MR Head, L. Zhu, Headway Technologies, Inc., p351.
4B.5 A Study of ESD Sensitivity of AMR and GMR Recording Heads, C. Lam, C. Chang, R. Karimi, Read-Rite Corporation, p360.
4B.6 Electromagnetic Interference (EMI) Damage To Giant Magnetoresistive (GMR) Recording Heads, A. Wallash, Quantum Corporation; D. Smith, Auspex Corporation, p368.
4B.7 Measurement of the Effects of Ionizer Imbalance and Proximity to Ground in MR Head Handling, L.Levit, Ion Systems; A. Wallash, Quantum Corporation, p375.
