1999 EOS/ESD Symposium
Orlando, FL
Table of Contents
Session 1A: Power Electronics and Device Behavior
Session Moderator: Steve Voldman, IBM
1A.1 Analysis and Compact Modeling of Lateral DMOS Power Devices Under ESD Stress Conditions, M. Mergens, W. Wilkening, S. Mettler, Robert Bosch, GmbH; H. Wolf, Fraunhofer-Institut (IZM); A. Stricker, W. Fichtner, Swiss Federal Institute of Technology (ETHZ), p1
1A.2 Investigations on Double-Diffused MOS (DMOS) transistors under ESD zap conditions, G. Boselli, T. Mouthaan, University of Twente; F. Kuper, S. Meeuwsen, Philips Semiconductors Nijmegen, p11.
1A.3 Wide Range Control of the Sustaining Voltage of ESD Protection Elements Realized in a Smart Power Technology, H. Gobner, T. Moller-Lynch, K. Esmark, M. Stecher, lnfineon Technologies, p19.
1A.4 Analyzing the Switching Behavior of ESD-Protection Transistors by Very Fast Transmission Line Pulsing, H. Wolf, Technische Universitat Munchen; H. Gieser, Fraunhofer-Institute Zuverlassigkeit in der Microsystemtechnik; W. Wilkening, Robert Bosch, GmbH, p28.
1A.5 Invited Paper: Plasma-charging damage and ESD, help each other?, K.P. Cheung, Bell Laboratories, Lucent Technologies, p38.
Session 1B: Electrostatic Considerations
Session Moderator: Joseph Bernier, Harris Semiconductor
1B.1 A Study of ESD Induced Lockups in a Semiconductor Photolithography Area, Ford-Smith, Ion Systems; H. Barnett, G. Leal, G. Sutorius, Motorola, p43.
1B.2 PAPERWITHDRAWN, p48.
IB.3 Electrostatic Test Methods Compared, R. Gompf, NASA; P. Holdstock, British Textile Technology Group; J. Chubb, John Chubb Instrumentation, p49.
IB.4 Charging and Ignition of Sprayed Fuel, K. Davies, MARKAB; S. Gerken, USAF, p54.
Session 2A: On-Chip Protection
Session Moderator: Michael Chaine, Micron Technology
2A.1 An Anti-Snapback Circuit Technique for Inhibiting Parasitic Bipolar Conduction During EOS/ESD Events, J. Smith, Motorola, p62.
2A.2 Stacked PMOS Clamps for High Voltage Power Supply Protection, T. Maloney, W. Kan, Intel Corporation, p70.
2A.3 Invited Paper: A Study of Fully Silicided 0.18um CMOS ESD Protection Devices, T. Suzuki, S. Mitarai, S. Ito, H. Monma, N. Higashi, Fujitsu VLSI Ltd., (Best Paper RCJ 1998 EOS/ESD Symposium, Japan), p78.
2A.4 ESD Protection under Wire Bonding Pads, W. Anderson, Compaq Computer Corporation; W. Gonzalez, W. Fowler, Intel; S. Knecht, NeuMath, Inc., p88.
2A.5 Influence of gate length on ESD-performance for deep sub micron CMOS technology , K. Bock, B. Keppens, V. De Heyn, G. Groeseneken, IMEC; L.Y. Ching, A. Naem, National Semiconductor S., p95.
2A.6 Electrostatic Discharge (ESD) Protection in Silicon-on-insulator (SOI) CMOS Technology with Aluminum and Copper Interconnects in Advanced Microprocessor Semiconductor Chips , S. Voldman, D. Hui, L. Warriner, D. Young, J. Howard, F. Assaderaghi, G. Shahidi, IBM, p105.
2A.7 A Simulation Analysis of Quarter-Micron CMOS LSI Input Circuit Behavior under CDM-ESD for Protection Device Improvement, K. Narita, Y. Horiguchi, K. Hayano, K. Suzuki, NEC Corporation, p116.
Session 2B: Factory Level EOS/ESD
Session Moderator: Willard Y. McFarland, Lucent Technologies
2B.1 Measurement of Ionizer Performance - a New Approach, Levit, G.G. Desai, Ion Systems; W. Vosteen, Monroe Electronics, p124.
2B.2 PAPER WITHDRAWN, p130.
2B.3 Balanced Static Elimination in Variable Ion Mobility Environments, C.G. Noll, ITW Static Control and Air Products, p131.
2B.4 A Study of ESD, R. Vermillion, ARP Engineering; L. Fromm, Hewlett-Packard Company, p145.
2B.5 Conductive Floor and Footwear System as Primary Protection Against Human Body Model ESD, L. Seng, Siemens Components (AT) Sdn. Bhd., p155.
2B.6 Latent ESD Failures in Schottky Barrier Diodes, Y. Anand, D. Crowe, M/A-Com Inc., p160.
2B.7 Test Methodologies for Detecting ESD Events in Automated Processing Equipment, A. Steinman, Ion Systems; J. Bernier, Harris Semiconductor-, D. Boehm, Novx Corporation; T. Albano, Eastman Kodak Co.; W. Tan, Advanced Micro Devices; D. Pritchard, TREK, Inc., p168.
Session 3A: Device Level ESD Standards, Techniques and Methods
Session Co-Moderators: Leo G. Henry, ORYX Instruments Corporation and Warren Anderson, Compaq Computer Corporation
3A.1 Developing a Transient Induced Latch-up Standard for Testing Integrated Circuits, M. Kelly, Delphi Delco Electronics Systems; L.G. Henry, ORYX Instruments Corporation; J. Barth, Barth Electronics, Inc.; G. Weiss, Lucent Technologies; M. Chaine, Micron Technology, Inc.; H. Gieser, D. Bonfert, Fraunhofer-Institute Reliability and Micronintegration (IZM); T. Meuse, KeyTek; V. Gross, IBM Microelectronics; C. Hatchard, I. Morgan, Advanced Micro Devices, p178.
3A.2 Transient Latch-Up Using an Improved Bi-polar Trigger, I. Morgan, M. Mahanpour, Advanced Micro Devices; C. Hatchard, ORYX Instruments Corporation, p190.
3A.3 Issues Concerning CDM ESD Verification Modules-The Need to Move to Alumina, L.G. Henry, ORYX Instruments Corporation; M. Kelly, Delphi Delco Electronics Systems; T. Diep, Texas Instruments; J. Barth, Barth Electronics, p203.
3A.4 A Strategy for Characterization and Evaluation of ESD Robustness of CMOS Semiconductor Technologies, S.Voldman, IBM; W. Anderson, Compaq Computer Corp.; R. Ashton, Lucent Technologies; M. Chaine, Micron Technology, Inc.; C. Duvvury, Texas Instruments; T. Maloney, Intel Corp.; E. Worley, Conexant Semiconductor, p212.
3A.5 Design Methodoigy of a Robust ESD Protection Circuit for STI Process 256Mb NAND Flash Memory, T. lkehashi, K. Imamiya, K. Sakui, Toshiba Corporation, p225.
3A.6 ESD Performance Optimization of Ballast Resistor On Power AlGaAs/GaAs Heterojunction Bipolar Transistor Technology, C. Chu, G.P. Li, University of California; W.J. Ho, H.Y. Hsu, T-M Kao, C. Hua, D. Day, Network Device, Inc. , p235.
3A.7 lnterferometric Temperature Mapping during ESD Stress and Failure Analysis of Smart Power Technology ESD Protection Devices, C. Forbock, D. Pogany, M. Lizenberger, E. Gornik, Institute for Solid State Electronics; N. Seliger, Siemens AG-, H. Gobner, T. Moller-Lynch, M. Stecher, W. Werner, Infineon Technologies, p241.
Session 3B: EOS/ESD Materials Technology
Session Moderator: Steve Fowler, Fowler Associates
3B.1 Innovative ESD Thermoplastic Composites Structured Through Melt Flow Processing, M. Narkis, Technion - Institute of Technology; G. Lidor, A. Vaxman, L. Zuri, CarmelStat, p251.
3B.2 Investigating the Performance of Conductive Thick Epoxy Floors, M. Golane, Wolfgang Warmbier, p260.
3B.3 Processable ESD Control Materials Filled With Tunable Intrinsically Conductive Polymer Nanocomposites, J. Avlyanov, M. Cooper, Eeonyx Corporation; S. Dahman, RTP Company, p268.
3B.4 Effects of Aging, Wiping and Humidity on Surface Resistivity of Polyethylene and Polyproyiene Boxes, T. Lesniewski, TRW, p276.
3B. 5 Development of Accierated Aging Test for ESD/EMI Protective Materials and Electrical Discontinunity at Seams and Interconnections, R. Haynes, Richard Haynes Consultants, p282.
3B.6 Electrostatic Discharge (ESD) Mechanism for Battery Charge Contact Failure in
Cordless Phones, R. Coyle, M-C. Jon, Lucent Technologies Bell Laboratories, p287.
Session 3C (Poster Session): Magnetic Recording
Heads ESD Issues in Manufacturing and Test
Session Moderator: Jenny Himle, Maxtor
3C.1 Fields and ESD Risk from Charged Object Introduction into Hard Drives, B. Perry, Maxtor, p293.
3C.2 ESD Testing of Head Stack Assemblies Used in Magnetic Recording Hard Disk Drives, A. Wallash, Quantum Corporation, p297.
3C.3 The Real CDM Field Induced ESD Waveform from MR Heads, L.G. Henry, B. Hall, ORYX Instruments Corp., p302.
3C.4 ESD Testing of GMR Heads as a function of Temperature, C.Moore, Integral Solutions International; A. Wallash, Quantum Corporation, p309
3C.5 ESD Protection of GMR Heads in Manufacturing, F.J. Wu, X.M. Wang, R. Zeng, H. Tian, SAE Magnetics (HK) Ltd., p315.
3C.6 Analysis of the Electrical Field Effects of AC and DC Ionization Systems for MR Head Manufacturing, C. Newburg, River's Edge Technical Service, p319.
Session 4A: System Level EOS/ESD
Moderator: Jon Barth, Barth Electronics
4A.1 Unusual Forms of ESD and Their Effects, D. Smith, Auspex Systems, Inc., p329.
4A.2 PAPER WITHDRAWN, p334.
4A.3 An Improved Model of Man for ESD Applications, V. Amoruso, M. Heiali, F. Lattarulo, Politecnico di Bari, p335.
4A.4 Investigation of a Test Methodology for Triboelectrification, W. Greason, University of Western Ontario, p344.
4A.5 Hardware/Firmware Co-Design in an 8-Bits Microcontroller to Solve the System-Level ESD Issue on Keyboard, M.D. Ker, Y.Y. Sung, Industrial Technology Research Institute (ITRI), p352.
Session 4B: Magnetic Recording Heads ESD Technologies
Moderator: Jenny Himle, Maxtor
4B.1 Using HGA Antennas to Measure EMI; Establishing and Correlating Damage Thresholds of GMR Heads, B. Perry, J. Himle, T. Porter, W. Boone, J. LeBlanc, Maxtor, p361.
4B.2 ESD Damage by Directly Arcing to a MR Head, L.Y. Zhu, Headway Technologies, Inc. p367.
4B.3 A Study of Head Stack Assembly Sensitivity to ESD, W. Boone, J. Himle, T. Porter, B. Perry, Maxtor, p373.
4B.4 ESD Damage of GMR Sensors at Head Stack Assembly, R. Zeng, Y. Qun, F. Zhao, H. Tian, SAE Magnetics (HK) Ltd. p380.
4B.5 A Study of Diode Protection for Giant Magnetoresistive Recording Heads, A. Wallash, Quantum Corporation; W. Wang, lomega Corporation, p385.
4B.6 ESD Sensitivity Study of GMR Recording Heads with a Flex-On-Suspension Head-Gimbal Assembly, C. Lam, D. Martinez, C. Chang, Read-Rite Corporation, p391.
Workshop Session A
Workshop Chairman: Michael Chaine, Micron Technology
A.1 Electrostatics and ESD in Magnetic Recording, Moderator: Al Wallash, Quantum Corporation, 405.
A.2 System Level ESD, Moderator: Doug Smith, Auspex Systems, p406.
A.3 ESD Control Program and Audit Problems,Moderator: Larry Fromm, Hewlett Packard, p407.
A.4 On-Chip Protection, Moderator: Eugene Worley, Conexant Systems, p408.
Workshop Session B
Workshop Chairman: Michael Chaine, Micron Technology
B.1 ESD in Cleanrooms, Moderator: Tom Albano, p409.
B.2 Failure Mechanism and Solutions for On-Chip Circuits and ESD Networks, Moderator: Steve Voldman, IBM, p410.
B.3 ESD Testing of High Pin Count Devices, Moderator: Warren Anderson, Compaq Computer Corporation, p411.
B.4 ESD Material and Reliability, Moderator: Richard Haynes, Richard Haynes Consultants, p412.
