2000 EOS/ESD Symposium
Anaheim, CA
Table of Contents
Session 1A: Novel ESD Circuits and Structures
Session Moderator: Warren Anderson, Compaq Computer Corporation
IA.1 Invited Paper: A Study of Wafer Level ESD Testing, K. Yokoi, T. Watanabe, NEC Corporation, (Best Paper RCJ 1999 EOS/ESD Symposium, Japan), p1.
1A.2 Substrate Pump NMOS for ESD Protection Applications, C. Duvvury, S. Ramaswamy, A. Amerasekera, R. Cline, B. Andresen, V. Gupta, Texas Instruments, p7.
IA.3 Wafer Cost Reduction through Design of High Performance Fully Silicided ESD Devices, K. Verhaege, C. Russ, Sarnoff Corporation, p18.
1A.4 Silicon-On-insulator Dynamic Threshold ESD Networks and Active Clamp Circuitry, S. Voldman, J. Howard, M. Sherony, F. Assaderaghi, IBM Semiconductor Research and Development Center; D. Hui, D. Young, D. Dreps, IBM Corporation; G. Shahidi, IBM T.J. Watson Research Center, p29.
Session 1B: Systems
Session Moderator: Douglas Smith, D. C. Smith Consultants
1 B.1 Optimizing The Performance of a Composite ESD Circuit Protection Device, H. Hyatt, Littelfuse, Inc. and Hyger Physics, Inc.; J. Harris, J. Colby, Littelfuse, Inc.;P. Bellew, Littelfuse, Ireland Ltd., p41.
IB.2 ESD Immunity in System Designs, System Field Experiences and Effects of PWB Layout, D. Smith, D.C. Smith Consultants; E. Nakauchi, Garwood Labboratories, Inc., p48.
I B.3 Generalized Model of Electrostatic Discharge (ESD) for Bodies in Approach: Analyses of Multiple Discharges and Speed of Approach, W. Greason, University of Western Ontario, p54.
1B.4 Detecting ESD Events using a Loop Antenna, J. Muhoz, J. Tan, C. Adriano, E. Roldan, Intel Technology Philippines Incorporated, p60.
Session 2A: Device Level ESD Standards, Methods, and Techniques
Session Moderator: Leo G. Henry, ESD/TLP Consulting
2A.1 Influence of the Charging Effect on HBM ESD Device Testing, T. Brodbeck, lnfineon Technologies AG, p66.
2A.2 The Importance of Standardizing CDM ESD Test Head Parameters to Obtain Data Correlation, L.G. Henry, EDS/TLP Consulting; M. Kelly, Delphi Delco Electronics Systems; T. Diep, Texas Instruments; J. Barth, Barth Electronics, Inc., p72.
2A.3 TLP Calibration, Correlation, Standards, and New Techniques, J. Barth, J. Richner, Barth Electronics Inc; K. Verhaege, Sarnoff Corporation: L.G. Henry, ESD/TLP Consultant, p85.
2A.4 A Method for Determining a Transmission Line Pulse Shape that Produces Equivalent Results to Human Body Model Testing Methods, J. Lee, M. Hoque, J. Liou, University of Central Florida; G. Croft, W. Young, J. Bernier, Intersil Corporation, p97.
2A.6 Comparison and Correlation of ESD HBM (Human Body Model) Obtained Between TLPG, Wafer-Level, and Package-Level Tests, M. Lee, C. Liu, C-C Lin, J-T Chou, H. Tang, Y. Chang, K. Fu, United Microelectronics Corp., p105.
2A.6 TLP Measurements for Verification of ESD Protection Device Response, H. Hyatt, Littelfuse & Hyger Physics, Inc.; J. Harris, A. Alanzo, Littelfuse, Inc.; P. Bellew, Littelfuse, Ireland, p111.
Session 2B: Materials
Session Co-Moderators: Joe Bernier, Intersil Corporation and Stephen Koehn, 3M Corporation
2B.1 Invited Paper: Conductive Materials for ESD Applications: An Overview, R. Rosner, 3M Electronics Handling & Protection Division, p121.
2B.2 Advancements in Inherently Dissipative Polymer (IDP) Alloys Provide New Levels of Clean, Consistent ESD Protection, K. Kim, N. Hardwick, H. Pham, T. Fahey, BFGoodrich Static Control Polymers, p132.
2B.3 Controlling ESD and Cleanliness by Using New Thermoplastic Compounds for Injection Molded and Corrugated Packaging Products, M. Narkis, Technion - Institute of Technology; G. Lidor, A. Vaxman, L. Zuri, Carmel Olefins Ltd., p139.
2B.4 New Methods for Measuring Resistance and Charge decay of Worksurfaces, H. Uchida, H. Kurosaki, T. Numaguchi, Sumitomo 3M Limited, p152.
2B.5 Mechanical and Electrical Properties of Poly (ether ether ketone) (PEEK) with Various Conductive Fillers, C. Extrand, Entegris, p161.
2B.6 Evaluation of Materials Used in Cleanrooms with ESD Sensitive Hardware, T. Lesniewski, K. Yates, TRW Space and Electronics Group, p166.
Session 2C (Poster Session): Magnetic Recording
Session Moderator: Jenny Himle, Maxtor Corporation
2C.1 Limitations of the Adiabatic Model for ESD Failure in GMR Structures, E. Granstrom, N. Tabat, Seagate Recording Head Operations, p180.
2C.2 A Case Study on Hidden ESD Events of GMR HGA Dynamic Test Fixture, R. Bordeos, J. Kagaoan, Shenzhen Kaifa Technology Co. Ltd., p184.
2C.3 A Study of Methods to Eliminate Metal Contact in GMR Head Manufacturing, H. Snyder, Technical Consulting Associates; A. Wallash, Quantum Corporation, p190.
2C.4 Advances in Magneto Optical Static Event Detector Technology, N. Jacksen, ExMod Corporation; L. Nelsen, D. Boehm, Novx Corporation; T. Odom, VCD Technologies, p193.
2C.5 The Effect of Bonding Sequence on GMR ESD Protection, Zhao, R. Tao, H. Tian, SAE Magnectics (HK) Ltd., p202.
2C.6 HDA-Level ESD Testing of Giant Magnetoresistive (GMR) Recording Heads, D. Nordin, Quantum Corporation, p205.
2C.7 PAPER WITHDRAWN, p211.
2C.8 Evaluation of Tribocharging and ESD Protection Schemes on GMR Magnetic Recording Heads During C02 Jet Cleaning, D. Vickers, D. Carradero, Quantum Corporation, p212.
2C.9 Measuring and Specifying Limits on Current Transients and Understanding Their Relationships to MR Head Damage, W. Ogle, C. Moore, Integral Solutions, Int'l., p207.
2C.10 The Effects of EMI from Cell Phones on GMR Magnetic Recording Heads and Test Equipment, V. Kraz, Credence Technologies, Inc.; A. Wallash, Quantum Corporation, p224.
2C.11 Investigation of ESD Transient EMI Causing Spurious Clock Track Read Transitions During Servo-Write, B-C Yap, Western Digital (Malaysia) Sdn. Bhd.; C. Patton, Senergy Co., p233.
Session 3A: Silicon Germanium, RF BiCMOS/CMOS
and CMOS Technology
Session Co-Moderators: Eugene Worley, Conexant Corporation and Jeremy Smith, Motorola
3A.1 Electrostatic Discharge Characterization of Epitaxial-Base Silicon-Germanium Heterojunction Bipolar Transistors, S. Voldman, N. Schmidt, R. Johnson, L. Lanzerotti, A. Joseph, C. Brennan, J. Dunn, D. Harame, IBM Semiconductor Research and Development Center; P. Juliano, E. Rosenbaum, University of Illinois at Urbana-Champaign; B. Meyerson, IBM T.J. Watson Reserch, p239.
3A.2 Investigation on Different ESD Protection Strategies Devoted to 3.3 V RF Applications (2 GHz) in a 0.18 pm CMOS Process, C. Richier, P. Salome, G. Mabboux, I. Zaza, A. Juge, P. Mortini, STMicroelectronics, p251.
3A.3 ESD Protection in Fully-Depleted CMOS/SIMOX with a Tungsten-Clad Source/Drain, H. Koizumi, Y. Komine, Y. Ohtomo, M. Shimaya, NTT Telecommunications Energy Laboratories, p260.
3A.4 On-Chip ESD Protection Design by Using Polysilicon Diodes in CMOS Technology for Smart Card Applications, T. Wang, Sunplus Technology Co. Ltd.; M-D Ker, National Chiao-Tung University, p266.
3A.5 Invited Paper: Hot Carrier Degradation and ESD in Submicron CMOS Technologies: How Do They Interact?, G. Groeseneken, IMEC, p276.
3A.6 Breakdown and Latent Damage of Ultra-Thin Gate Oxides under ESD
Stress Conditions, J. Wu, P. Juliano, E. Rosenbaum, University of Illinois at Urbana-Champaign, p287.
3A.7 High Current Characteristics of Devices in a 0.18 pm CMOS Technology, E. Worley, A. Salem, Y. Sittampalam, Conexant Systems, p296.
3A.8 EngineeringtheCascodedNMOSOutputBufferforMaximumVtl., J. Miller, M. Khazhinsky, J. Weldon, Motorola, Inc., p308.
Session 3B: Magnetic Recording
Session Moderator: Chung Lam, Read-Rite, Inc.
3B.1 ESD Damage Thresholds: History and Prognosis, B. Perry, Maxtor Corporation, p318.
3B.2 ESD Sensitivity of GMR Heads at Variable Pulse Length, D. Guarisco, M. Li, Maxtor Corporation, p322.
3B.3 Threshold of ESD Damage to GMR Sensor, R. Tao, FG Zhao, SAE Magnecics (HK) Ltd., p327.
3B.4 Charge Induction on GMR Recording Heads Caused by AC Power Fields, M. Honda, Impulse Physics Laboratory, Inc., p330.
3B.5 Considerations for an HBM ESD Standard for Measuring and Testing of Magneto Resistive Heads, L. Henry, ESD/TLP Consultant; A. Wallash, Quantum Corporation, p337.
3B.6 A Comparison of Quasi-Static Characteristics and Failure Signatures of GMR Heads subjected to CDM and HBM ESD Events, C. Moore, Integral Solutions, lnt'l., p343.
3B.7 In-situ Spin Stand ESD Testing of Giant Magnetoresistive (GMR) Recording Heads, A. Wallash, Quantum Corporation, p349.
3B.8 Baseline Popping of Spin-Valve Recording Heads Induced by ESD, Y. Shen, R. Leung, J. Sun, SAE Magnetics (HK) Ltd., p355.
Session 3C: Factory Issues
Session Moderator: Willard McFarland, Lucent Technologies
3C.1 Invited Paper: ESD Control in the Factory of the Future or 20.20 to the Rescue, D. Swenson, 3M Electronics Handling & Protection Division, p360.
3C.2 Device Charging in Shipping Packages, B. Unger, Burt Unger Associates, p361.
3C.3 Designing and Testing of Facilities Ground, D. Stockin, Lyncole Industries, Inc., p368.
3C.4 Corrosion Induced Electrostatic Damage., J. Franey, Lucent Technologies Bell Labs, p375.
3C.5 Measurement Technique Developed to Evaluate Transient EMI in a Photo Bay With and Without Air Ionization, A. Rudack, M. Pendley, International SEMATECH; L. Levit, Ion Systems, p379.
3C.6 Random GaAs IC's ESD Failures Caused by RF Test Handier, Y. Anand, D. Crowe, A. Feinberg, C. Jones, M/A-COM, Incorporated, p387.
3C.7 A Study of the Mechanisms for ESD Damage to Reticles, J. Montoya, Intel Corporation; L. Levit, Ion Systems; A. Englisch, Dupont Photomasks, p394.
3C.8 PAPER WITHDRAWN, p406.
Session 4A: CMOS Technology and Modeling
Session Co-Moderators: Christian Russ, Sarnoff Corporation and Stephen Beebe, AMD
4A.1 A Novel NMOS Transistor for High Performance ESD Protection Devices in a 0.18 um CMOS Technology Utilizing Salicide Process, C-S Kim, H-B Park, Y-G Kim, D-G Kang, M-G Lee, S-W Lee, C-H Jeon, H-G Kim, Y-J Yoo, H-S Yoon, Hyundai Electronics Industries Co. Ltd., p407.
4A.2 ESD Performance of Bridge-Resistance Pressure Diaphragm Sensors, K-L Lei, C. Chu, J. Tseng, Y-M Chiang, M. Young, Advanced Custom Sensors, Inc.; G. Li, University of California, p413.
4A.3 Advanced2D/3DESDDeviceSimulation-ApowerfulToolAireadyUsed in a Pre-Si Phase, K. Esmark, W. Stadler, M. Wendel, H. GoBner, X. Guggenmos, Infineon Technologies AG; W. Fichtner, ETH Zurich, p420.
4A.4 Electrothermal Modeling of ESD Diodes in Bulk-Si and SOI Technologies, Y. Wang, P. Juliano, S. Joshi, E. Rosenbaum, University of Illinois at Urbana-Champaign, p430.
4A.5 A Scalable Analytical Model for the ESD N-Well Resistor, V. Puvvada, V. Srinivasan, V. Gupta, Texas Instruments (India) Ltd., p437.
4A.6 ESD-level Circuit Simulation - Impact of Gate RC-Delay on HBM and CDM Behavior, M. Mergens, Bosch (now with Sarnoff Corporation); W. Wilkening, G. Kiesewefter, S. Mettler, J. Hieber, Robert Bosch GmbH; H. Wolf, Fraunhofer-Institut for Zuverlaessigkeit un Mikrointegration (IZM); W. Fichtner, Swiss Federal Institute of Technology (ETHZ), p446.
4A.7 Chip-Level Simulation for CDM Failures in Multi-Power ICs, J. Lee, S. Kang, University of Illinois; Y. Huh, J-W Chen, P. Bendix, LSI Logic Corporation, p456.
4A.8 Verify ESD: A Tool for Efficient Circuit Level ESD Simulations of Mixed-Signal lCs, M. Baird, Arizona State University and Motorola; R. Ida, Motorola, p465.
Session 4B: Magnetic Recording II
Session Moderator: Hong Tian, SAE Magnetics (HK) Ltd.
4B.1 ESD Evaluation of Tunneling Magnetoresistive (TMR) Devices, A. Wallash, J. Hillman, Quantum Corporation; D. Wang, Nonvolatile Electronics, p470.Inc.
4B.2 Wafer Charging in Process Equipment and Its Relationship to GMR Heads
Charging Damage, W. Lukaszek, Wafer Charging Monitors, Inc., p475.
4B.3 Floating Gate EEPROM as EOS Indicators During Wafer-Level GMR Processing, E. Granstrom, R. Cermak, P. Tesarek, N. Tabat, Seagate Recording Head Operations, p481.
4B.4 Investigation of GMR sensor microstructural changes induced by HBM ESD using advanced Microscopy Approach, R. Bordeos, Z. Lianzhu, Shenzhen Kaifa Technology Co. Ltd.; S. Hung, C. Wong, The Hong Kong University of Science & Technology, p485.
4B.5 A Study of Static Dissipative Tweezers for Handling Giant Magneto-Resistive Recording Heads, C. Lam, Read-Rite Corporation, p491.
4B.6 PAPER WITHDRAWN, p498
4B.7 Electrostatic Voltmeter and Fieldmeter Measurements on GMR Recording Heads, D. Pritchard, Trek Incorporated, p499.
4B.8 Effect of I nS to 250 mS ESD Transients on GMR Heads, S. Ramaswamy, J. Carter, J. Stubbart, A. Singh, R. Krasnick, MKPA/Panasonic; F. Gocemen, MKPNPanasonic (now with Quantum Corporation), p505
