2002 EOS/ESD Symposium
Charlotte, NC
Table of Contents
Session 1A: On-Chip Protection
Moderator: Marise Bafleur, LAAS-CNRS
1A.1 New Considerations for MOSFET Power Clamps, S. S. Poon, T. J. Maloney, Intel Corporation
1A.2 New ESD Protection Circuits Based on PNP Triggering SCR for Advanced CMOS Device Applications, Y. Morishita, NEC Corporation
1A.3 High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune IC Operation, M. P. J. Mergens, C. C. Russ, J. Armer, P. C. Jozwiak, R. Mohn, Samoff Corporation; K. G. Verhaege, Sarnoff Europe
1A.4 A 6mW, 1.5dB NF CMOS LNA for GPS with 3kV HBM ESD-Protection, P. Leroux, M. Steyaert, K. U. Leuven; V. Vassilev, H. Maes, K. U. Leuven and IMEC
Session 1B: Systems Issues
Moderator: Jon Barth, Barth Electronics, Inc.
IB.1 Sources of Impulsive EMI in Large Server Farms, D. C. Smith, D. C. Consultants; L. G. Henry, M. Hogsett, Ion Systems; J. Nuebel, Sun Microsystems
1B.2 Electromagnetic Interference (EMI) Inside a Hard Disk Drive Due to External ESD, D. C. Smith, D. C. Smith Consultants; A. Wallash, Maxtor Corporation
1B.3 Experimental Investigation of the Electrostatic Discharge (ESD) Characteristics for the Charged Human Body Handling Circuit Packs, W. D. Greason, University of Western Ontario
1B.4 A Study of Flip-Flop IC Upset Exposed by ESD Radiated Fields, M. Honda, Impulse Physics Laboratory, Inc.
Session 2A: RF ESD Design and Technology
Moderators: Gene Worely, Conexant Systems, and Richard Ida, Motorola SPS
2A.1 Variable-Trigger Voltage ESD Power Clamps for Mixed Voltage Applications Using a 120 GHz/100 GHz (fT/fMAX) Silicon Germanium Heterojunction Bipolar Transistor with Carbon Incorporation, S. Voldman, IBM Communications Research and Development Center (CRDC)
2A.2 Optimization of Input Protection Diode for High Speed Applications, E. R. Worley, A. Bakulin, Conexant Systems
2A.3 Harnessing the Base-Pushout Effect for ESD Protection in Bipolar and BICMOS Technologies, M. Streibl, K. Esmark, A. Sieck, W. Stadler, M. Wendel, J. Szatkowski, H. Gollner, Infineon Technologies.
2A.4 A Novel On-Chip ESD Protection Circuit for GaAs HBT RF Power Amplifiers, Y. Ma, G. P. Li, University of California
2A.5 Test Methods, Test Techniques and Failure Criteria for Evaluation of ESD Degradation of Analog and Radio Frequency (RF) Technology, S. Voldman, A. Van Laecke, J. Rascoe, L. Lanzerotti, D. Sheridan, IBM Microelectronics Division; B. Ronan, S. Ames, Princeton University
2A.6 Technology CAD Evaluation of BICMOS Protection Structures Operation Including Spatial Thermal Runaway, V. Vashchenko, A. Concannon, M. Ter Beek, P. Hopper, NSC
2A.7 Modeling and Extraction of RF Performance Parameters of CMOS Electrostatic Discharge Protection Devices, V.Vassilev, G.Groeseneken, S.Jenei, H. Maes, IMEC and KUUESAT; R.Venegas, IMEC; M.Steyaert, KUL/ESAT
Session 2B: MR Device Issues
Moderators: Ferruh Goceman, Maxtor Corporation, and Eric Granstrom, Seagate Technology
2B.1 Invited Paper: Analysis of Barkhausen Noise Failure Caused by ESD in a GMR Head, T. Hamaguchi, T. Ichihara, T. Ohtsu, Hitachi, Ltd., (Best Paper RCJ 2001 EOS/ESD Symposium, Japan)
2B.2 Effects of ESD Transients on the Properties of GMR Heads, E. Granstrom, H. Cho, S. Stokes, S. Srun, N. Tabat, Seagate Technology
2B.3 High Frequency Instabilities in GMR Heads Due to Metal-to- Metal Contact ESD Transients, H. Patland, W. Ogle, Integral Solutions Int'l
2B.4 A Study of Electrostatic Discharge on MR Heads in Digital Tape Systems, Y. Soda, K. Kasuga, T. Ozue, Sony Corporation
2B.5 Tribocharging and Electrical Breakdown at the Magnetic Recording Head-Disk Interface J. Himle, A. Wallash, Maxtor Corporation
2B.6 Magnetoresistive Sensitivity Mapping (MSM) and Dynamic Electrical Test (DET) Correlation Study on GMR Sensor Induced by Low Threshold ESD Stress, S. T. Hung, C.Y. Wong, The Hong Kong University of Science and Technology; R. Bordeos, L. Z. Zhang, Shenzhen Kaifa Technology Co. Ltd.
Session 3A: Transmission Line Pulsing and Standardization
Moderator: Leo G. Henry, Ion Systems, Inc.
3A.1 Correlation Considerations II: Real HBM to HBM testers, J. Barth, J. Richner, Barth Electronics, Inc.; K. Verhaege, Sarnoff Europe; M. Kelly, Delphi Delco Electronics Systems; L. G. Henry, Ion Systems, Inc.
3A.2 A New ESD Model: The Charged Strip Model, A, Olney, A. Righter, D. Belisle, E. Cooper, Analog Devices, Inc.
3A.3 ESD: Standards, Threats and System Hardness Fallacies, H. Hyatt, Hyger Physics, Inc
3A.4 A Study of High Current Characteristics of Devices in a 0.13m m CMOS Technology, P-Y Tan, 1. Manna, Y-C Tan, K-F Lo, P-H Li, Chartered Semiconductor Mfg. Ltd.
3A.5 ESD Degradation Analysis of Poly-Si N-type TFT Employing TLP (Transmission Line Pulser) Test, B-C Jeon, S-C Lee, M-C Lee, K-C Moon, J-K Oh, M-K Han, Seoul Nat'l University
3A.6 The ESD Preventive Measure Based on the Excessive Mobile Charge for Advanced Electron Devices and Production Lines, K. Suzuki, M. Sato, NEC Corporation
Session 3B: Factory and Materials
Moderator: Donn Bellmore, Universal Instruments Corporation
3B.1 An Automated Test of Tribocharging for Automotive Seating Fabric, A. DeAngelis, K. Green, Milliken & Company; G. Yezersky, Daimler-Chrysler Corporation
3B.2 Triboelectric Testing at KSC Under Low Pressure and Temperature, R. Gompf, NASA
3B.3 Controlling ESD in Automated Handling Equipment, D. G. Bellmore, Universal Instruments Corporation
3B.4 ESD Protection Materials Using Conductive Polymers, K. S. Suh, J. E. Kim, Korea University and lnscon Tech.; T. Y. Kim, Korea University; K. S. Moon, H. S. Moon, Y. K. Park, Samsung Electronics
3B.5 Noise Reduction of Corona Discharge Air Ionizer, T. Terashige, Hiroshima International University; D. Ohashi, K. Okano, The Polytechnic University
3B.6 Biological Aspects of Clean-Room Ionization, P. Gefter, Ion Systems
3B.7 ESD Control Tools for Surface Mount Technology and Final Assembly Lines, J. Passi, P. Tamminen, T. Kalliohaka, H. Kojo, K. Tappura, VTT Industrial Systems
Session 3C: Simulation and Modeling
Moderator: Christian Russ, Sarnoff Corporation
3C.1 Efficient pnp Characteristics of PMOS Transistors in Sub- 0.13 m m ESD Protection Circuits, G. Boselli, C. Duvvury, V. Reddy, Texas Instruments Inc.
3C.2 ESD Protection by Keep-On Design for a 550 V Flourescent Lamp Control IC with Integrated LDMOS Power Stage, J. van Zwol, A. van den Berg, T. Smedes, Philips Semiconductors
3C.3 Effect of the n+Sinker in Self-Triggering Bipolar ESD Protection Structures, V. De Heyn, N. lyer, G. Groeseneken, IMEC & K. U. Leuven; K. Reynders, P. Moens, Alcatel Microelectronic
3C.4 Design Guidelines to Achieve a Very High ESD Robustness in a Self-Biased NPN, D. Tremouilles, LAAS-CNRS and ON Semiconductor-, G. Bertrand, L. Lescouzeres, ON Semiconductor; M. Bafleur, N. Nolhier, LAAS-CNRS
3C.5 Compact Modeling of Vertical ESD Protection NPN Transistors for RF Circuits, S. Joshi, E. Rosenbaum, University of Illinois at Urbana-Champaign
3C.6 An Automated Electrostatic Discharge Computer-Aided Design System with the Incorporation of Hierarchical Parameterized Cells in BICMOS Analog and RF Technology For Mixed Signal Applications, S. Voldman, S. Strang, D. Jordan, IBM Communications Research and Development Center (CRDC)
Session 4A - MR Factory Issues
Moderators: Ferruh Goceman, Maxtor Corporation, and Eric Granstrom, Seagate Technology
4A.1 Standardized Direct Charge Device Model ESD Test For Magnetoresistive Recording Heads I, T. Cheung, ReadRite Corporation; L. Baril, A. Wallash, Maxtor Corporation
4A.2 Standardized Direct Charge Device Model ESD Test For Magnetoresistive Recording Heads II, L. Baril, A. Wallash, Maxtor Corporation; T. Cheung, ReadRite Corporation
4A.3 The Practical Approach of ESD Control Solution in Headstack Assembly (HSA) Manufacturing, R. Bordeos, Shenzhen Kaifa Technology Co. Ltd.
4A.4 Impact of Insulating "Conductive" Materials on Disk Drive ESD Robustness, B. Perry, T. Porter, W. Boone, Maxtor Corporation
4A.5 ESD Damage by Arcing near GMR Heads, Z. Y. Teng, Y. G. Wang, W. Li, R. Tao, SAE Magnetics (HK) Ltd.
4A.6 Effect of GMR Recording Head Resistance on Human Body and Machine Model ESD Waveforms, A. Lai, SAE Magnetics (HK) Ltd.; A. Wallash, Maxtor Corporation
4A.7 Study for Recover Process of Damaged Al203 during Ion Milling to Increase Tolerance to ESD, S. Kakuta, S. Odai, K. Furusawa, Hitachi, Ltd.
Session 4B: Device Effects
Moderator: Craig Salling, Texas Instruments
4B.1 Investigations for a Smart Power and Self-Protected Device Under ESD Stress Through Geometry and Design Considerations for Automotive Applications, P. Besse, LAAS-CNRS and Motorola Semiconductors Toulouse; M. Zelcd, Motorola Semiconductors Toulouse; N. Nolhier, M. Bafieur, LAAS-CNRS; Y. Chung, Motorola Semiconductors
4B.2 The Impact of Substrate Resistivity on ESD Protection Devices, T. Smedes, J. van Zwol, P. C. de Jong, Philips Semiconductors; A. Heringa, Philips Research Laboratories
4B.3 ESDCharacterizationofGrounded-GateNMOSwithO.35m m/18VTechnology Employing Tranmission Line Pulser (TLP) Test, B-C Jeon, S-C Lee, J-K Oh, S-S Kim, M-K Han, Seoul Nat'l University; Y-1 Jung, H-T So, J-S Shim, K-H Kim, Hynix Semiconductor Inc.
4B.4 Process Influence on Product CDM ESD Sensitivity, B. Lisenker, Intel Israel
4B.5 Copper Interconnect Microanalysis and Electromigrabon Reliablity Performance due to the Impact of TLP ESD, S. C. K. Sherry, P-Y Tan, E-C Chua, S-C T. Carol, 1. Manna, S. Redkar, S. Ansari, Chartered Semiconductor Mfg. Ltd.
4B.6 Investigation of ESD Protection Elements Under High Current Stress in CDM-Like Time Domain Using Backside Laser lnterferometery, S. Bychikhin, V. Dubec, M. Litzenberger, D. Pogany, E. Gornik, Vienna University of Technology; G. Groos, K. Esmark, M. Stecher, W. Stadler, Infineon Technologies; H. Gieser, H. Wolf, Fraunhofer
Institute
Workshop Session A
Workshop Chair: Dale Parkin, IBM
A.1 ESD in Magnetic Recording, Moderator: Ferruh Goceman, Maxtor Corporation
A.2 S20.20 ESD Control Program Certification, Moderator: Ron Gibson, Celestica, Inc.
A 3 On-Chip Protection for RF Technologies, Moderator: Richard Ida, Motorola SPS
A.4 ESD in Cleanrooms, Moderator: Tom Albano, Eastman Kodak Company
Workshop Session B
Workshop Chair: Dale Parkin, IBM
B.1 System Level ESD Considerations, Moderator: Douglas Smith, D.C. Smith Consultants
B.2 Transmission Line Pulse Testing (TLP) - Ideas and Applications, Moderator: Natarajan Mahadeva lyer, IMEC
B.3 Auditing Measurements According to ESD Association Standards Test Methods, Moderator: Kimberly Becker, Prostat Corporation
